1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to methods and structure relating to through wafer vias.
2. Background Art
Through waver vias (TWVs), also known as through silicon vias (TSVs), have dimensions that are relatively large compared to other structures in current IC chip technology. For example, TWVs have dimensions on the order of 4 micrometers (μm) wide by 10 μm long. The large width results in a very high local pattern factor during chemical mechanical polish (CMP) of the TWVs at the contact level. Consequently, severe topography (approximately 100 nanometers (nm) or greater) may result due to dishing or erosion during CMP. For aluminum-copper (AlCu) back-end-of-line (BEOL) structures this situation is not an issue since the sub-etch AlCu process fully removes the AlCu films. For a damascene copper (Cu) process, however, this situation presents a problem because the topography causes the tantalum liner or copper (Ta/Cu) deposition to result in large puddles of material, causing shorts. A secondary issue with advanced BEOL technologies, such as 130 nm or beyond, is that titanium nitride and tungsten (TiN/W) metallization processes used for the TWVs cannot simultaneously fill both the TWV and the standard contacts.